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19-1212; Rev 0; 3/97
MAX3680 Evaluation Kit
_______________General Description
The MAX3680 evaluation kit (EV kit) simplifies evaluation of the MAX3680 622Mbps, SDH/SONET 1:8 deserializer. The EV kit requires only a +3.3V supply, and includes all the external components necessary to interface with 3.3V PECL/TTL logic. The board can be connected directly to the output of a clock-and-data-recovery circuit (such as the MAX3675) and to the TTL input of an overhead termination circuit. It can also be used with a signal generator and an oscilloscope to evaluate the MAX3680's basic functionality.
____________________________Features
o Single +3.3V Supply o Inputs Terminated for Interfacing with 3.3V PECL o Outputs Configured for 50 or High-Impedance Interface o Fully Assembled and Tested
Evaluates: MAX3680
______________Ordering Information
PART MAX3680EVKIT-SO TEMP. RANGE -40C to +85C BOARD TYPE Surface Mount
____________________Component List
DESIGNATION QTY C1-C4 C5 4 1 DESCRIPTION 0.1F ceramic capacitors 33F, 10V tantalum capacitor AVX TAJC336K010 or Sprague 293D336X0010C2 2.2F tantalum capacitor AVX TAJA225K010 or Sprague 293D225X0010A2 100pF ceramic capacitors SMA connectors (PC edge mount) 56nH inductor Coilcraft 0805CS-560-XKBC 82, 5% resistors 130, 5% resistors 2.4k, 5% resistors 2-pin headers MAX3680EAI MAX3680 data sheet
_______________Detailed Description
The MAX3680 EV kit simplifies evaluation of the MAX3680 622Mbps, SDH/SONET 1:8 deserializer. The EV kit operates from a single +3.3V supply and includes all the external components necessary to interface with 3.3V PECL/TTL logic. Each PECL input (SCLK+, SCLK-, SD+, SD-) is terminated on the EV board with the Thevenin equivalent of 50 to (VCC - 2V). These inputs can be driven directly by any 3.3V PECL device's output, such as a clockand-data-recovery circuit (e.g., the MAX3675). The synchronization input (SYNC) is a TTL input. The TTL outputs (PCLK, PD_) can interface to either 50 or high-impedance inputs. To interface to 50 inputs, connect the inputs directly to the SMA connectors labeled PCLK and PD0-PD7. This configuration forms a 50-to-1 voltage divider that maintains a highimpedance load to each TTL output while interfacing to 50. To interface to high-impedance inputs, connect the inputs to the 2-pin headers at R9-R17, which provide direct connections to the TTL outputs.
C6 C7-C12 J3-J16 L1 R1, R3, R5, R7 R2, R4, R6, R8 R9-R17 +3.3V, GND JR9-JR17 U1 None
1 6 14 1 4 4 9 11 1 1
______________Component Suppliers
SUPPLIER AVX Coilcraft Sprague PHONE (803) 946-0690 (847) 639-6400 (603) 224-1961 FAX (803) 626-3123 (847) 639-1469 (603) 224-1430
_____________Layout Considerations
To minimize propagation-delay skew, all PECL input signal lines are 50 transmission lines of equal length. To allow accurate characterization of the parallel-clock to data-output delay, the output data lines (prior to the series 2.4k termination resistors) are matched and kept as short as possible. Excluding the series termination resistor, each output data line measures approximately 3pF at the 2-pin header (JR9-JR17).
Please indicate that you are using the MAX3680 when contacting the above component suppliers.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
Evaluates: MAX3680
R17 2.4k J9 PD7 R16 2.4k J10 PD6 JR2 JR1
MAX3680 Evaluation Kit
Figure 1. MAX3680 EV Kit Schematic
1 VCC VCC SD+ PD6 U1 R4 130 R3 82 C2 0.1F 26 GND 27 PD7 C1 0.1F R1 82 VCC 3 2 VCC J4 SDSDVCC PD5 JR3 6 SCLK+ GND 23 24 R15 2.4k VCC J11 PD5 5 C3 0.1F R5 82 VCC J6 SCLKSCLKPD4 JR4 8 VCC PD3 GND PD2 VCC PD1 GND VCC PD0 19 18 17 16 15 JR8 R10 2.4k 14 J16 PD0 JR7 JR6 R11 2.4k J15 PD1 20 GND SYNC GND GND PCLK 9 J7 SYNC 11 12 13 10 21 JR5 R12 2.4k J14 PD2 7 22 R8 130 R7 82 R14 2.4k C4 0.1F J12 PD4 R13 2.4k J13 PD3 4 VCC 25 28
2
VCC
J3
R2 130
SD+
MAX3680
VCC
J5
R6 130
SCLK+
J8 PCLK
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE ZO = 50
_______________________________________________________________________________________
L1 +3.3V C5 33F 10V C6 2.2F 10V 56nH C7 100pF C8 100pF C9 100pF C10 100pF C11 100pF C12 100pF VCC GND
MAX3680 Evaluation Kit Evaluates: MAX3680
1.0"
1.0"
Figure 2. MAX3680 EV Kit Component Placement Guide
Figure 3. MAX3680 EV Kit PC Board Layout--Component Side*
1.0"
1.0"
Figure 4. MAX3680 EV Kit PC Board Layout--Bottom Silkscreen*
*Not to scale
Figure 5. MAX3680 EV Kit PC Board Layout--Solder Side*
_______________________________________________________________________________________
3
MAX3680 Evaluation Kit Evaluates: MAX3680
1.0"
1.0"
Figure 6. MAX3680 EV Kit PC Board Layout--GND Plane*
Figure 7. MAX3680 EV Kit PC Board Layout-- Power Plane*
*Not to scale
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
4 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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